Vector modulators utilizing frequency synthesizers are well known in the art, and are utilized in various applications. In conventional modulators, the baseband signal is converted to an analog signal by means of a digital-to-analog converter and is then mixed with a synthesized carrier by means including the use of an image rejection mixer. The use of sigma delta based fractional-N synthesizers in such modulator designs is becoming more common.
A typical prior art fractional N synthesizer is illustrated in FIG. 1. Referring to FIG. 1, the synthesizer comprises a reference frequency generator 10 (e.g. a crystal oscillator) for generating a reference frequency, Fo. The reference frequency generator 10 is coupled to a frequency divider circuit 12 so as to allow the frequency signal Fo to be divided down by a factor of R to a desired value. The output of the frequency divider 12 is then coupled to a phase-lock loop circuit 14 comprising a phase-detector 16, a filter 15, a voltage controlled oscillator 18 (VCO) and a variable divider circuit 20.
The synthesizer further includes a fractional control circuit 21 or interpolator coupled to the variable divider circuit 20. In operation, the fractional control circuit 21 controls the variable divider circuit 20 such that the divider alternately divides the VCO output 18 by a factor of N, or a factor of N+1. By controlling the rate by which the VCO output is divided by N or N+1, it is possible to generate an output signal, whose average value is a desired faction of N. Typically, the fractional control circuit 21 comprises an accumulator having a predetermined/programmable modulo (i.e., capacity) and bit length, which is determined in accordance with the desired fractional output. In response to each pulse output by the variable divider circuit 20, the accumulator is incremented, and when the accumulator overflows, it generates a carry signal. The carry signal is coupled to the variable divider circuit 20 and utilized to determine whether or not the variable divider circuit 21 should divide by a factor of N or N+1. An example of the operation of the accumulator is illustrative. Assuming it is desired to generate a frequency output equal to (N+0.25)Fo/R, the accumulator is programmed so as to generate a carry bit every fourth pulse. As such, the variable divider circuit 21 will operate to divide by N for 3 pulses and divide by N+1 every fourth pulse. As a result, output frequency of the synthesizer equals (N+0.25)Fo/R.
Notwithstanding the ability of known frequency synthesizers to generate output signals having a fractional value of “N”, in order to obtain exceedingly fine resolution, prior art synthesizers still require the use of direct digital synthesizers to provide for exceedingly fine tuning/resolution. However, as direct digital synthesizers are expensive and generate unwanted spurious/noise signals, it is desirable to eliminate the need for the direct digital synthesizer from the design. In addition, it is desirable to provide for direct modulation of the carrier of the frequency synthesizer so as to allow for the elimination of digital-to-analog converters, image rejection mixers and RF filters from the design, all of which are required with conventional modulation schemes. The elimination of the foregoing components results in a significant cost savings.
Accordingly, there exists the need for a vector modulator that eliminates all of the foregoing problems.